1. Field of the Invention
The present invention relates to fabricating a memory device. In particular, the present invention provides a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, and a semiconductor substrate in the recess gate region is etched to prevent a silicon horn in the recess gate region from being formed, thereby increasing a margin of the etching process. Although the present invention has been applied to a specific memory device, there can be other applications.
2. Discussion of the Related Art
FIG. 1 is a simplified layout of a conventional semiconductor device.
Referring to FIG. 1, a semiconductor substrate having a device isolation film 40, an active region 10a and a gate structure 120 as a word line crossing over the active region 10a is formed on a semiconductor substrate. The line width of the gate structures 120 is F, which is a minimum line width according to the design rule. A line-type recess gate region 60 is disposed under the gate structure 120. The line width of the recess gate region 60 is smaller than that of the gate structure 120 by 2D. That is, a misalignment margin of the recess gate region 60 is D.
FIGS. 2a through 2f are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2a(i) through 2f(i) are cross-sectional views taken along the line I–I′ of FIG. 1, and FIGS. 2a(ii) through 2f(ii) are cross-sectional views taken along the line II–II′ of FIG. 1.
Referring to FIG. 2a, a pad oxide film 20 and a pad nitride film 30 are deposited on the semiconductor substrate 10. Next, a device isolation film 40 defining an active region 10a is formed via an STI process.
Referring to FIG. 2b, the device isolation film 40 is etched to lower the height of the device isolation film 40. The nitride film 30 is then removed. Next, a polysilicon layer 50 is formed on the entire surface.
Referring to FIG. 2c, a photoresist film (not shown) is formed on the polysilicon layer 50, and then exposed and developed using an exposure mask defining the recess gate region 60 of FIG. 1 to form a line-type mask pattern (not shown) exposing the recess gate region 60 to be formed. Next, the exposed polysilicon layer 50 and the pad oxide film 20 are etched using the mask pattern as an etching mask to form a polysilicon layer pattern 50a and a pad oxide film pattern 20a defining the recess gate region 60. Thereafter, the mask pattern is removed.
Referring to FIG. 2d, the exposed semiconductor substrate 10a is etched using the polysilicon layer pattern 50a as an etching mask to form a recess gate region 70. Here, the etching process is performed to simultaneously etch the semiconductor substrate 10 and the polysilicon layer pattern 50a. At this time, the etching rate of the semiconductor substrate 10 adjacent to the device isolation film 40 is slower than that of the semiconductor substrate 10 spaced apart from the device isolation film 40, thereby forming a silicon horn ‘A’ on the semiconductor substrate 10 within the recess gate region 70. Next, the pad oxide film pattern 20a is removed.
Referring to FIG. 2e, a gate oxide film 80 is formed on the surface of the exposed semiconductor substrate 10. Thereafter, a lower gate electrode layer 90 filling up the recess gate region 70 is formed on the entire surface. An upper gate electrode layer 100 and a hard mask layer 110 are then sequentially deposited on the lower gate electrode layer 90.
Referring to FIG. 2f, the hard mask layer 110, the upper gate electrode layer 100 and the lower gate electrode layer 90 are patterned to form a gate structure 120 consisting of a stacked structure 120 of a lower gate electrode 90a, an upper gate electrode 100a and a hard mask layer pattern 110a. 
FIG. 3 is a cross-sectional view illustrating misalignment occurring between the gate structure and the recess gate region in accordance with the conventional method for fabricating a semiconductor device.
Referring to FIG. 3, in case of misalignment occurring between a recess gate mask and a gate mask with M, which is larger than D, the misalignment margin, the semiconductor substrate under the lower gate electrode is etched in the subsequent etching process. The gate oxide film on an upper corner of the etched semiconductor substrate is degraded. In addition, concentration in one of storage node contact regions is less than that of the other in the subsequent process for forming LDD and S/D (source/drain) regions due to unbalanced recess channel region under the gate structure, thereby increasing resistance of a cell transistor adjacent to the storage node contact region having the lower concentration. As a result, operation speed of the cell transistor could slow down.
FIG. 4 is a cross-sectional view illustrating misalignment occurring in the recess gate region in accordance with the conventional method for fabricating a semiconductor device.
Referring to FIG. 4, in case of misalignment occurring between a recess gate mask and a device isolation film mask with M larger than D, the semiconductor substrate adjacent to a device isolation film is exposed as well as M-D. The exposed semiconductor substrate is simultaneously etched in the etching process of FIG. 2d. The exposed semiconductor substrate where the storage node contact in DRAM Cell is to be formed is a critical region for leakage current characteristics. The above etching of the semiconductor substrate induces increase in the leakage current, thereby degrading the refresh characteristics of DRAM.
Moreover, as shown in FIG. 2d, the etching rate of the semiconductor substrate adjacent to the device isolation film relatively slows, so that the silicon horn remains on the semiconductor substrate adjacent to the device isolation film. Accordingly, the threshold voltage of the cell transistor is decreased, thereby increasing the leakage current.